Extensive assessment of the charge-trapping kinetics in InGaAs MOS gate-stacks for the demonstration of improved BTI reliability

Putcha, Vamsi; Franco, Jacopo; Vais, Abhitosh; Kaczer, Ben; Xie, Qi; Maes, Jan Willem; Tang, Fu; Givens, Michael; Collaert, Nadine; Linten, Dimitri; Groeseneken, Guido

doi:10.1016/j.microrel.2020.113996

Extensive assessment of the charge-trapping kinetics in InGaAs MOS gate-stacks for the demonstration of improved BTI reliability

Author:

Putcha, Vamsi

Franco, Jacopo ; Vais, Abhitosh ; Kaczer, Ben ; Xie, Qi ; Maes, Jan Willem ; Tang, Fu ; Givens, Michael ; Collaert, Nadine ; Linten, Dimitri ; Groeseneken, Guido

Keywords:

Science & Technology, Technology, Physical Sciences, Engineering, Electrical & Electronic, Nanoscience & Nanotechnology, Physics, Applied, Engineering, Science & Technology - Other Topics, Physics, Bias Temperature Instability (BTI), InGaAs, Gate-stack reliability, NMP theory, Defect-band modelling, Total operating voltage range, Capture/Emission Time (CET) maps, ASM-IL, Opposite-Arrhenius-temperature-dependence, 0906 Electrical and Electronic Engineering, Applied Physics, 4009 Electronics, sensors and digital hardware