Design and qualification of a MGy tolerant front - end chip in 65 nm CMOS for the read - out of remotely operated sensors and actuators during maintenance in ITER

Verbeeck, Jens; Cao, Ying; Van Uffelen, Marco; Mont Casellas, Laura; Damiani, Carlo; Ruiz Morales, Emilio; Ranz Santana, Roberto; Meek, Richard; Haist, Bernhard; Hamilton, David; Steyaert, Michiel; Leroux, Paul

Design and qualification of a MGy tolerant front - end chip in 65 nm CMOS for the read - out of remotely operated sensors and actuators during maintenance in ITER

Author:

Verbeeck, Jens

Cao, Ying ; Van Uffelen, Marco ; Mont Casellas, Laura ; Damiani, Carlo ; Ruiz Morales, Emilio ; Ranz Santana, Roberto ; Meek, Richard ; Haist, Bernhard ; Hamilton, David ; Steyaert, Michiel ; Leroux, Paul

Abstract:

This paper describes the radiation qualification procedure for a 1 MGy-tolerant Application Specific Integrated circuit ( ASIC) developed in 65 nm CMOS technology. The chip is intended for the read-out of electrical signals of sensors and actuators during maintenance in ITER. First the general working principle of the ASIC is shown. The developed IC allows to read-out, condition and digitize multiple low bandwidth (<10 kHz) sensors. In addition the IC is able to multiplex the digitized sensor signals. To comply with ITER-relevant constraints an adapted radiation qualification procedure has been proposed. The radiation-qualification procedure describes the test criteria and test conditions of the developed ASICs, which are also compared with COTS alternatives, to meet the stringent qualification procedures for electronics exposed to radiation in ITER.