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Ieee Security & Privacy

Publication date: 2020-06-30
Pages: 178 - 193
Publisher: Institute of Electrical and Electronics Engineers

Author:

Purnal, Antoon
Giner, Lukas ; Gruss, Daniel ; Verbauwhede, Ingrid

Keywords:

Cathedral - 695305;info:eu-repo/grantAgreement/EC/H2020/695305, C16/15/058#53326573, 0802 Computation Theory and Mathematics, 0803 Computer Software, 0804 Data Format, Strategic, Defence & Security Studies, 4604 Cybersecurity and privacy

Abstract:

Recent secure cache designs aim to mitigate side-channel attacks by randomizing the mapping from memory addresses to cache sets. As vendors investigate deployment of these caches, it is crucial to understand their actual security. In this paper, we consolidate existing randomization-based secure caches into a generic cache model. We then comprehensively analyze the security of existing designs, including CEASER-S and ScatterCache, by mapping them to instances of this model. We tailor cache attacks for randomized caches using a novel PRIME+PRUNE+PROBE technique, and optimize it using burst accesses, bootstrapping, and multi-step profiling. PRIME+PRUNE+PROBE constructs probabilistic but reliable eviction sets, enabling attacks previously assumed to be computationally infeasible. We also simulate an end-to-end attack, leaking secrets from a vulnerable AES implementation. Finally, a case study of CEASER-S reveals that cryptographic weaknesses in the randomization algorithm can lead to a complete security subversion. Our systematic analysis yields more realistic and comparable security levels for randomized caches. As we quantify how design parameters influence the security level, our work leads to important conclusions for future work on secure cache designs.