Author:

Keywords:

Science & Technology, Technology, Physical Sciences, Engineering, Electrical & Electronic, Nanoscience & Nanotechnology, Physics, Applied, Engineering, Science & Technology - Other Topics, Physics, Single-event effects, Circuit layout, Charge sharing, Heavy ions, Monte-Carlo simulation, SOFT ERROR, COMBINATIONAL-CIRCUITS, 0906 Electrical and Electronic Engineering, Applied Physics, 4009 Electronics, sensors and digital hardware

Abstract:

© 2018 Elsevier Ltd For nanometer technologies, SET is increasingly growing in importance in circuit design. Accordingly, different hardening techniques were developed to reduce the Soft-Error Rate. Considering selective node hardening technique based on standard cells, this work evaluates the SET response of logic gates from a Standard-Cell library under heavy ions. Overall, it is observed that the usage of NOR and NAND gates coupled with an output inverter provides reduced SET cross-section and increased threshold LET compared with the standalone OR gate and AND gate, respectively. With the results gathered in this work, circuit designers can implement reliability-aware synthesis algorithms with selective hardening more efficiently to tackle the threat of SET in combinational circuits.