Author:

Keywords:

Science & Technology, Physical Sciences, Technology, Electrochemistry, Metallurgy & Metallurgical Engineering, Physics, Condensed Matter, Physics, INTERCONNECTS, TECHNOLOGY

Abstract:

In advanced CMOS technology, the RC delay and Cu barrier reliability of interconnects are both key parameters that need to be carefully tuned for optimal device performance. One way of achieving this is to reduce the effective resistance of the Cu lines by decreasing the cross-sectional area occupied by the barrier metal. To reach this objective, a two-step approach is taken. We first consider the possibility of using the Ionized Physical Vapor Deposition (I-PVD) process by selecting the type of barrier layer and optimizing its thickness and conformality in trenches patterned in Aurora® ULK, a porous low-k film deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD). This appears to be successful up to approximately 15nm barrier thickness as measured in the field area. To further decrease the barrier thickness, while preserving conformality and integrity without degrading RC delay, it appears necessary to consider the possibility of using for instance an atomic layer deposited (ALD) barrier (e.g. WN x C y ). From RC delay perspective, the benefit of the process is demonstrated. However, its implementation is far more complex. A number of key properties such as porosity, bulk diffusion of barrier precursors have to be taken into consideration and studied in relation with surface sealing and subsequent barrier deposition by ALD. Furthermore, given the importance of the starting surface for this type of barrier, a more fundamental study of WN x C y growth on the different surfaces seen by the precursors during integration is mandatory. These key issues for device integration are investigated using X-ray reflectivity (XRR). © 2004 Materials Research Society.