Author:

Keywords:

algorithm and architecture co-optimization, signal processing, cmos, transceiver

Abstract:

In this work, we identify the new challenges which arise when implementing digital intensive transceivers for multi-mode communications. Multi-mode transceivers require analog front-ends that operate well over a large number of frequency bands, challenging the frequency mixing and increasing the sensitivity to timing and amplitude mismatches. To tackle these new challenges, we bring system architecture together with digital signal processing (DSP) algorithm and architecture design to obtain a better understanding of the key tradeoffs of performance metrics. We carry out the studies for the following three concrete cases. Timing mismatches of parallel mixing paths limits the achievable harmonic rejection (HR) performance in a multi-mode transceiver design. This thesis proposes a digital intensive multi-path mixing architecture and an iterative mismatch calibration method aiming at joint calibration for transmitter (Tx) and receiver (Rx), using on-chip loopback and a dedicated test signal. The proposed architecture and calibration scheme enables high HR performance in presence of substantial timing mismatches. Although a digital intensive multi-path mixing architecture can improve HR performance, it significantly increases design challenges in the radio frequency digital-to-analog converter (RFDAC) blocks in the digital transmitter. This thesis presents a low-cost one-current RFDAC architecture, which migrates the LO mixing operation to the digital domain, and allows to cut the required number of current cells in RFDAC by half at the cost of the increased sensitivity to timing mismatch problem. To enable the one-current RFDAC architecture, an effective predistortion scheme based on a run-time binary-tree descent searching scheme is proposed to tackle the timing mismatch problem in the one-current RFDAC architecture. Finally, an optimized and power-efficient implementation of the proposed timing correction scheme is presented. To also apply the RFDAC architecture for millimeter-wave communication, and tackle the problems in the traditional analog-centric polar transmitter, we propose a new digital-intensive transmitter architecture with polar concept expanded to the whole transmitter. Further, this work optimizes the digital frontend for a polar transmitter working in the 60 GHz band. As a very high bandwidth is available at 60 GHz, a digital frontend operates at very high frequency, which can easily become the bottleneck in the system power budget if not optimized carefully. The systematic optimizations are first explored to minimize the design requirements on the digital frontend. An efficient latchbased pipeline is then studied to provide the required 7.04 Gsps throughput with power consumption of less than 60 mW. The synthesis results compare favorably with previously reported architectures. By exploring a digital intensive multi-path HR mixing architecture, a lowcost one-current RFDAC architecture and an energy efficient digital frontend processor for 60 GHz polar transmtter, this thesis contributes to more energy efficient and high-performance wireless communications systems that can be implemented in the deeply-scaled Silicon technologies.