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Abstract:

© 2001 Non IEEE. Implementation of a charge trapping layer in the dielectric of Metal-Oxide- Semiconductor (MOS) structures provides a means for realizing Quasi-Non-Volatile- Memory (Q-NVM) cells. We fabricated MOS capacitors containing a Silicon-Rich- Oxide (SRO) layer with excess Silicon content ranging between 10 and 19.5 at%. Capacitance-Voltage characteristics exhibit a large hysteresis, shifting the flatband voltage over circa 6 V. The flatband voltage window collapses gradually over time. SRO layers with the lowest amount of excess Silicon have the best retention performance, with a flatband voltage difference of 2.45 V after 10,000 s and an extrapolated collapse of the window at 7.4 years.