Author:

Keywords:

Science & Technology, Technology, Engineering, Electrical & Electronic, Engineering, analog-digital conversion, CMOS analog integrated circuits, sigma-delta modulation, switched-capacitor circuits, A/D CONVERTER, TECHNOLOGY, MODULATOR, GAIN, 0204 Condensed Matter Physics, 0906 Electrical and Electronic Engineering, 1099 Other Technology, Electrical & Electronic Engineering, 4009 Electronics, sensors and digital hardware

Abstract:

The design of a high-resolution, high-speed, delta-sigma analog-to-digital converter that operates from a single 3.3-V supply is presented. This supply voltage presents several design problems, such as reduced signal swing and nonzero switch resistance in the switched-capacitor circuits. These problems are tackled in this design by a careful optimization at the system level and by a detailed analysis of several circuit nonidealities. The converter uses a 2-1-1 cascade topology with optimized coefficients. For an oversampling-ratio of only 24, the converter achieves a signal-to-noise ratio of 87 dB, a signal-to-(noise + distortion) ratio of 82 dB, and an input dynamic range of 15 bits after comb filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for asymmetrical digital subscriber line applications of 1.1 MHz. It is implemented in a 0.5-μm CMOS technology, in a 5-mm2 die area, and consumes 200 mW from a 3.3-V power supply.