ITEM METADATA RECORD
Title: Bias Temperature Instability Effects in Devices with Fully-Silicided Gate Stacks, Strained-Si and Multiple-Gate Architectures (Instelpunt-temperatuurs-instabiliteits- en mechanische spanningseffecten in transistoren met volledig gesilicideerde en meervoudige poortarchitecturen)
Other Titles: Bias Temperature Instability Effects in Devices with Fully-Silicided Gate Stacks, Strained-Si and Multiple-Gate Architectures
Authors: Shickova, Adelina; M0333827
Issue Date: 3-Dec-2008
Table of Contents: Contents

Chapter I: Introduction 23
I.1. CMOS Device Scaling 23
I.2. Objectives of the thesis 29
I.3. Structure of the thesis 30
Chapter II: State-of-the-Art Experimental Techniques 30
Chapter III: Reliability of Devices with Fully Silicided Gate Stacks 30
Chapter IV: Reliability of Strained-Si Devices 30
Chapter V: Reliability of Devices with Multiple-Gate Architectures 31
Chapter VI: Conclusions and Future Work 31
Bibliography 32

Chapter II: State-of-the-Art Experimental Techniques 37
II.1 Introduction 37
II. 2. Bias Temperature Instability 37
II.2.1. NBTI models 38
II.2.1.1. Reaction–Diffusion (R–D) model 38
II.2.1.2. Disorder-Controlled Kinetics model 39
II.2.2. Activation energy and time dependence 41
II.2.3. Interface traps and oxide charges 43
II.2.4. NBTI recovery 46
II.2.5. Nitrogen and fluorine 47
II.2.6. Wafer orientation 48
II.2.7. BTI measurement set-up 48
II. 3. Complementary Electrical Characterization Techniques 50
II.3.1. The conventional Charge Pumping (CP) 50
II.3.2. Conventional frequency sweep 52
II.3.3. Variable Tcharge-Tdischarge-Charge Pumping: VT2CP 52
II.3.4. Stress-Induced Leakage Current (SILC) 55
II.3.5. Low-frequency Noise 58
II.3.5.1 McWhorter's (DN) Surface Modulation Noise Mechanism 60
II.3.5.2. Hooge's (Dm) Mobility Fluctuation Mechanism 61
II.3.6. Time Dependent Dielectric Breakdown (TDDB) 62
II.3.6.1. Constant current stress (CCS) 63
II.3.6.2. Constant voltage stress (CVS) 63
II.3.6.3. TDDB analysis: the Weibull distribution 64
II. 4. Conclusions 67
Bibliography 68

Chapter III: Reliability of Devices with Fully Silicided Gate Stacks 77
III.1. Introduction 77
III.2. FUSI Process Flow 79
III.2.1. Ni silicide phase formation and effective work function 79
III.2.2. Scalability of Ni FUSI gate processes and device
implementation 82
III.2.3. Dual work function phase controlled Ni FUSI CMOS
integration scheme 86
III.2.4. Summary 89
III. 3. Reliability Studies 90
III.3.1. Motivation 90
III.3.2.Device Processing Details and Experimental Techniques 90
III.3.3. Experimental Results 91
III.3.3.1. Effect of Gate Electrode on NBTI 91
III.3.3.2. Effect o f Back-End-of-Line Thermal Budget on BTI 96
III.3.3.3.Effects of Nitridation Conditions on BTI 99
III.3.3.4. Observations on the scalability of the BTI behaviour
in sub-1nm EOT dielectrics 109
III. 4. Conclusions 111
Bibliography 113

Chapter IV: Reliability of Strained-Si Devices 119
IV. 1. Introduction 119
IV. 2. Transport Enhancement 121
IV.2.1. Electron mobility 121
IV.2.2. Hole mobility 122
IV.2.3. Piezoresistance coefficients 123
IV.2.4. Dangling bonds 126
IV. 3. Strain introduction techniques 127
IV.3.1. Stress-strain relationship 127
IV.3.2. Global strain substrates 127
IV.3.3. SiGe and Si:C Source/Drain 130
IV.3.4. Contact-Etch Stop Layers (CESL) 133
IV.3.5. Stress Memorization Technique (SMT) 136
IV. 4. Reliability Studies 137
IV.4.1. Motivation 137
IV.4.2. Device Processing Details and Experimental Techniques 138
IV.4.3. Experimental Results 140
IV.4.3.1. NBTI Characterization 140
IV.4.3.2. Charge pumping and noise measurements 145
IV.4.3.3. Impact of strain on carrier mobility in the
vertical direction 148
IV.4.3.4. Electron Spin Resonance (ESR) measurements 150
IV.4.3.5. Discussion 151
IV. 5. Conclusions 153
Bibliography 154

Chapter V: Reliability of Devices with Multiple-Gate Architectures 163
V.1. Introduction 163
V.2. Types of Multiple-Gate Devices 164
V.2.1. Planar Double-Gate devices 165
V.2.2. Tri-Gate devices 165
V.2.3. Vertical Double-Gate devices 165
V.2.4. W-Gate devices 165
V.2.5. Gate-All-Around (GAA) 165
V.2.6. P-Gate devices 166
V.2.7. Summary 167
V.3. Reliability Studies 168
V.3.1. Motivation 168
V.3.2. Device Processing Details and Experimental Techniques 169
V.3.2.1. Devices used in Section V.3.3.1:
(Effects of Corner Rounding on TDDB) 169
V.3.2.2. Devices used in Section V.3.3.2:
(Effects of Fluorine Passivation on BTI) 169
V.3.2.3. Devices used in Section V.3.3.3:
(Effects of Nitridation Techniques on BTI) 170
V.3.3. Experimental Results 171
V.3.3.1. Effects of Corner Rounding on TDDB 171
Sub-Section V.3.3.1.A. Devices without corner rounding 173
Sub-Section V.3.3.1.B. Devices with corner rounding 177
V.3.3.2. Effects of Fluorine Passivation on BTI 180
V.3.3.3. Effects of Nitridation Techniques on BTI 189
V.4. Conclusions 195
Bibliography 196

Chapter VI: Summary, Conclusions and Future Work 203
VI.1. Summary 203
VI.2. Main conclusions 203
VI.2.1. Reliability of Devices with Fully Silicided Gate Stacks 203
VI.2.2. Reliability of Strained-Si Devices 205
VI.2.3. Reliability of Devices with Multiple-Gate Architectures 206
VI.3. Future work 208
VI.3.1. Reliability of Devices with Fully Silicided Gate Stacks 208
VI.3.2. Reliability of Strained-Si Devices 208
VI.3.3. Reliability of Devices with Multiple-Gate Architectures 208

Curriculum Vitae 209
Publication status: published
KU Leuven publication type: TH
Appears in Collections:Associated Section of ESAT - INSYS, Integrated Systems
ESAT - MICAS, Microelectronics and Sensors

Files in This Item:
File Description Status SizeFormat
PhD_Thesis_Shickova_2008_final.pdf Published 4450KbAdobe PDFView/Open

 


All items in Lirias are protected by copyright, with all rights reserved.