Si-SiO2 interface trap densities have a dominant impact on the electrical performance of MOS devices and are playing a crucial role in the understanding of the underlying device physics, For bulk MOSFETs a large variety of techniques are applicable to determine the interface trap density. Most of them remain valid for low temperature device operation. For SOI MOSFETs however, transient effects have to be taken into account. This paper discusses a new and simple technique, based on the threshold voltage shift as a function of the operating temperature, to determine the interface trap density in fully depleted accumulation mode SOI devices operating at cryogenic temperature. The validity of the technique will be demonstrated for 77 K device operation.