Analog integrated circuits and signal processing vol:2 issue:4 pages:281-295
A method for the full on-chip analog implementation of large time constants in a CMOS technology is presented. These time constants are used for delayed synaptic transfer in neural networks for signal processing. For real-time speech recognition time constants from 1 to 500 ms are necessary, that vary logarithmically with a 4-bit digital code. An RC-type circuit is used to make a continuous time implementation. A modified operational transconductance amplifier (OTA) in a negative feedback configuration is used as a resistor and a gate-oxide capacitor is used as load. The output current of the OTA is divided by current dividers to obtain an electronic multiplication of the time constant. An adapted current mirror design is applied. Much attention is paid to offset-voltage reduction. This new multiplication scheme has several important advantages compared to other schemes. A global area minimization procedure is explained. The total active are of a 3-mum CMOS chip for a 500-ms time constant is 0.5 mm2. The realized circuit has a typical measured offset voltage of 130 mV. The area efficiency and the offset sensitivity are shown to be one order of magnitude better than in other designs.