Performance degradation induced by fringing field-induced barrier lowering and parasitic charge in double-gate metal-oxide-semiconductor field-effect transistors with high-kappa dielectrics
Autran, JL × Munteanu, D Houssa, Michel Castellani-Coulie, K Said, A #
Publication Board, Japanese Journal of Applied Physics
Japanese Journal of Applied Physics 1, Regular Papers, Short Notes & Review Papers vol:44 issue:12 pages:8362-8366
The electrical behavior of a decananometer double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with high-permittivity (high-kappa) and stacked-gate dielectrics has been investigated using two-dimensional (2D) quantum numerical simulation. We show that in spite of a quasi-ideal control of the channel by the gates in the double-gate structure, the device performances can be significantly degraded when using high-K dielectrics due to two important electrostatic limitations of high-kappa materials: i) the fringing field-induced barrier lowering effect (FIBL) and ii) the presence of discrete fixed charges in the gate stack. The FIBL compromises the performance of short-channel devices when simultaneously increasing the dielectric constant and its physical thickness, whereas the charges trapped in the high-kappa layer induce 2D potential fluctuations in the structure and degrades the subthreshold behaviour of the drain current.