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Title: Performance degradation induced by fringing field-induced barrier lowering and parasitic charge in double-gate metal-oxide-semiconductor field-effect transistors with high-kappa dielectrics
Authors: Autran, JL ×
Munteanu, D
Houssa, Michel
Castellani-Coulie, K
Said, A #
Issue Date: Dec-2005
Publisher: Publication Board, Japanese Journal of Applied Physics
Series Title: Japanese Journal of Applied Physics 1, Regular Papers, Short Notes & Review Papers vol:44 issue:12 pages:8362-8366
Abstract: The electrical behavior of a decananometer double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with high-permittivity (high-kappa) and stacked-gate dielectrics has been investigated using two-dimensional (2D) quantum numerical simulation. We show that in spite of a quasi-ideal control of the channel by the gates in the double-gate structure, the device performances can be significantly degraded when using high-K dielectrics due to two important electrostatic limitations of high-kappa materials: i) the fringing field-induced barrier lowering effect (FIBL) and ii) the presence of discrete fixed charges in the gate stack. The FIBL compromises the performance of short-channel devices when simultaneously increasing the dielectric constant and its physical thickness, whereas the charges trapped in the high-kappa layer induce 2D potential fluctuations in the structure and degrades the subthreshold behaviour of the drain current.
URI: 
ISSN: 0021-4922
Publication status: published
KU Leuven publication type: IT
Appears in Collections:Semiconductor Physics Section
× corresponding author
# (joint) last author

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