Title: A high-performance multibit Delta Sigma CMOS ADC
Authors: Geerts, Yves ×
Steyaert, MSJ
Sansen, Willy #
Issue Date: Dec-2000
Publisher: Ieee-inst electrical electronics engineers inc
Series Title: IEEE Journal of Solid-State Circuits vol:35 issue:12 pages:1829-1840
Abstract: The design of a multibit Delta Sigma converter is presented. It uses a third-order 4-bit Delta Sigma topology with data weighted averaging (DWA) to reduce the linearity requirements of the digital-to-analog converters in the feedback loop. The implementation of the DWA algorithm is optimized to minimize the delay introduced in the feedback loop, resulting in clock frequencies up to 100 MHz.
ISSN: 0018-9200
Publication status: published
KU Leuven publication type: IT
Appears in Collections:Electrical Engineering - miscellaneous
× corresponding author
# (joint) last author

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