IEEE Transactions on circuits and systems i-regular papers vol:54 issue:2 pages:268-279
For a current-steering digital-to-analog converter (DAC) without an extra output stage, the variation of the output voltage will result in the variation of the output delay. These output-dependent delay differences will deteriorate the spurious-free dynamic range (SFDR) of a high-speed high-accuracy DAC, especially when glitches exist. In this paper, a convenient mathematical model is presented to analyze during design the impact of this kind of delay differences on the SFDR. The results are verified by comparison to the results of more detailed simulations. Also the impact of glitches on this effect is demonstrated. Possible solutions to reduce this impact are discussed and summarized.