Lateral overgrowth of TiSi2 and CoSi2 films in VLSI circuits has been studied using a specially designed yield monitoring chip. The yield of a circuit in which CoSi2 has been employed can be significantly improved by performing the silicidation reaction in two steps. For both silicides the circuit yield may be improved by reducing the temperature of the first reaction in the silicidation scheme. However, the resultant sheet resistance of the TiSi2 is very sensitive to changes in this temperature. Circuit design has a major influence on yield with those circuits which have corners of polysilicon over silicon regions exhibiting lower yields. Circuit yield exhibits a strong dependence on spacer width and circuits with narrower spacers return lower yields.