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Title: Effects of lattice defects on degradation of flash memory cell
Authors: Kobayashi, K ×
Ohyama, H
Nakabayashi, M
Simoen, E
Claeys, Cor
Kudou, K
Yoneoka, M
Hayama, K
Kohiki, S #
Issue Date: 2000
Publisher: Trans tech publications ltd
Series Title: Beam injection assessment of microstructures in semiconductors, 2000 vol:78-79 pages:231-235
Abstract: Results are presented of a study on the effects of induced lattice defects on performance degradation of flash memory cells integrated in microcomputer by high-energy electrons and protons. A conventional stacked-gate n-channel flash memory cell using 0.8 mum n-polysilicon gate C technology on p-type 5-inch epitaxial. (100) Si wafer with typically 10 ohm-cm was used in this experiment with channel length of 0.8 mum and channel width of I Vm. The thickness of tunnel oxide is 12.5 nm and interpoly dielectric layer is ONO (Oxide: 1 run, Nitride: 12 run, Oxide: 9.5 mn) film. The memory cells are irradiated at room temperature by 1-MeV electrons and 20-MeV protons. After 10(3) times write and erase operations, Vth for write operation of irradiated memory cell decreases, while. it increases for erase operation. The change of Vth for proton irradiation is about two orders magnitude of larger than that for electron irradiation. The performance degradation is mainly caused by induced lattice defects in Si substrate, which are probably associated with divacancy, with tunnel oxide and interpoly dielectric layer.
ISSN: 1012-0394
Publication status: published
KU Leuven publication type: IT
Appears in Collections:Electrical Engineering - miscellaneous
Associated Section of ESAT - INSYS, Integrated Systems
× corresponding author
# (joint) last author

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