IEEE Journal of Solid-State Circuits vol:33 issue:12 pages:1959-1969
A 12-bit intrinsic accuracy digital-to-analog (D/A) converter integrated in a standard digital 0.5 mu m CMOS technology is presented. It is based on a current steering doubly segmented 6 + 2 + 4 architecture and requires no calibration, no trimming, or dynamic averaging. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 and 0.6 least significant bits (LSB's), respectively. The measured glitch energy is 1.9 pV - s, For a 12-bit resolution, the converter reaches an update rate of 300 MS/s. By reducing the voltage supply of the latches to 2.0 V, the glitch energy is reduced to sub-pV - s, and the update rate reaches 500 MS/s, for a resolution of 8 bits. The worst case power consumption is 320 mW, and it operates from a single 3.3 V voltage supply. The die area is 3.2 mm(2).