Title: Buffer memory requirements in DSP applications
Authors: Ade, M ×
Lauwereins, Rudy
Peperstraete, JA #
Issue Date: May-1999
Publisher: C r l publishing ltd
Series Title: Computer systems science and engineering vol:14 issue:3 pages:155-165
Abstract: In this paper, we study consistent synchronous multi-rate data flow graphs to determine the minimal required buffer sizes that still guarantee the construction of a deadlock-free static schedule. A graph is split up in chains and clusters that can be studied independently. We present the results for chains, as well as for the most frequent clusters. The results will be used in the rapid prototyping environment GRAPE-II in case the emulation hardware contains FPGAs, or when memory is critical.
ISSN: 0267-6192
Publication status: published
KU Leuven publication type: IT
Appears in Collections:Associated Section of ESAT - INSYS, Integrated Systems
× corresponding author
# (joint) last author

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