IEEE Journal of Solid-State Circuits vol:40 issue:3 pages:576-583
The design of a high-voltage output driver in a digital 0.25-mu m 2.5-V technology is presented. The use of stacked devices with a self-biased cascode topology allows the driver to operate at three times the nominal supply voltage. Oxide stress and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The proposed high-voltage architecture uses a switching output stage.