Ifip transactions a-computer science and technology vol:12 pages:703-709
Recent algorithms for timing verification that calculate the longest sensitizable path often perform inefficiently for complex circuits with subcircuits having reconvergent logic causing the presence of false paths. This paper presents new algorithms for exploiting hierarchy in statically sensitizable path analysis. The usefulness of the method is demonstrated with two complex modules having false paths and the most difficult ISCAS-85 benchmarks that have false paths. Depending on the complexity of the false paths within the circuit, speedups of several orders of magnitude are demonstrated while maintaining the accuracy of the LSP algorithm.