In current and future technologies, the leakage of the transistors is a major contributor to the total power dissipation. That effect is even reinforced in SRAM circuits because the matrix contains a high proportion of cells that are not accessed for extended periods of time. This paper presents a memory that by use of small granular control of the supply voltages can succeed in gaining at least a factor 10 in total power reduction. Using a distributed last stage of the SRAM decoder the stand-by and active cycle of the SRAM matrix can be controlled per word. This allows to selectively wake-Lip only the needed word and peripheral circuitry. When combined with monitoring and DC-DC conversion circuitry for the stand-by voltage, a closed loop system is attained that can minimise power consumption in the SRAM matrix. (c) 2005 Elsevier Ltd. All rights reserved.