High-K gate dielectrics like HfO2 and HfSiO(N) are considered for the replacement Of SiO2 and SiON layers in advanced complementary metal-oxide-semiconductor (MOS) devices. Using these gate oxides allows indeed to drastically reduce the leakage current flowing through the device, as required by the specifications of the International Technology Roadmap, for Semiconductors. However, major problems remain to be solved before the possible use of high-K gate dielectrics in integrated circuits. The purpose of this paper is to give an overview of the challenges and issues pertaining to high-K-based devices. Several issues are discussed in detail, like flat-band and threshold voltage control, carrier mobility degradation, charge trapping, gate dielectric wear-out and breakdown, and bias temperature instabilities. Our current understanding of these issues is presented, with an emphasis on the relationship between the material properties of the gate stack, and the electrical properties of the devices. The combination of metal gates with high-K gate dielectric appears to be a promising solution for the further scaling down of CMOS devices. (c) 2006 Elsevier B.V. All rights reserved.