Title: Methodology for building processor design space exploration
Authors: Barat, F
Vander Aa, Tom
Jayapala, Murali
Deconinck, Geert
Lauwereins, Rudy
Corporaal, Henk #
Issue Date: Mar-2007
Conference: Digest of the 3rd Workshop on Optimizations for DSP and Embedded Systems - ODES-3 date:20/03/07
Publication status: published
KU Leuven publication type: IC
Appears in Collections:ESAT - ELECTA, Electrical Energy Computer Architectures
Associated Section of ESAT - INSYS, Integrated Systems
# (joint) last author

Files in This Item:

There are no files associated with this item.

Request a copy


All items in Lirias are protected by copyright, with all rights reserved.