Symposium on VLSI Technology. Digest of Technical Papers, Date: 2005/06/14 - 2005/06/16, Location: Leuven Belgium
Publication date:
2005-01-01
Volume:
2005
Pages:
198 -
199
ISSN:
4-900784-00-1, 9784900784000
Publisher:
IEEE
2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS
Author:
Kottantharayil, Anil
Verheyen, Peter ; Collaert, Nadine ; Dixit, Abhisek ; Kaczer, Ben ; Snow, Jim ; Vos, Rita ; Locorotondo, Sabrina ; Degroote, Bart ; Shi, Xiaoping ; Rooyackers, Rita ; Mannaert, Geert ; Brus, Stephan ; Yim, Yong Sik ; Lauwers, Anne ; Goodwin, Michael ; Kittl, Jorge ; Van Dal, Mark ; Richard, Olivier ; Veloso, Anabela ; Kubicek, Stefan ; Beckx, Stephan ; Boullart, Werner ; De Meyer, Christina ; Absil, Philippe ; Jurczak, Malgorzata ; Biesemans, Serge
Keywords:
Science & Technology, Technology, Computer Science, Hardware & Architecture, Engineering, Electrical & Electronic, Computer Science, Engineering
Abstract:
We demonstrate a novel CMP-less dual hard mask scheme for the integration of fully suicided gates in FinFETs by simultaneous silicidation of the gate, source and the drain. V T of 0.18V and -0.2V are demonstrated for 50nm gate length NFET and PFET respectively. Competitive I ON-I OFF of 960uA/um-140nA/um for NFET and 620uA/um-100nA/um for PFET were obtained at V D=1.3V for an EOT of 1.8nm.