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Symposium on VLSI Technology. Digest of Technical Papers, Date: 2005/06/14 - 2005/06/16, Location: Leuven Belgium

Publication date: 2005-01-01
Volume: 2005 Pages: 106 - 107
ISSN: 4-900784-00-1
Publisher: IEEE

2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS

Author:

Witters, Liesbeth
Collaert, Nadine ; Nackaerts, Axel ; Demand, Marc ; Demuynck, Steven ; Delvaux, Christie ; Lauwers, Anne ; Baerts, Christina ; Beckx, Stephan ; Boullart, Werner ; Brus, Stephan ; Degroote, Bart ; de Marneffe, Jean-Francois ; Dixit, Abhisek ; De Meyer, Christina ; Ercken, Monique ; Goodwin, Michael ; Hendrickx, Eric ; Heylen, Nancy ; Jaenen, Patrick ; Laidler, David ; Leray, Philippe ; Locorotondo, Sabrina ; Maenhoudt, Mireille ; Moelants, Myriam ; Pollentier, Ivan ; Ronse, Kurt ; Rooyackers, Rita ; Van Aelst, Joke ; Vandenberghe, Geert ; Vandeweyer, Tom ; Vanhaelemeersch, Serge ; Van Hove, Marleen ; Van Olmen, Jan ; Verhaegen, Staf ; Versluijs, Janko ; Vrancken, Christa ; Wiaux, Vincent ; Willems, P ; Wouters, Johan MD ; Jurczak, Malgorzata ; Biesemans, Serge

Keywords:

Science & Technology, Technology, Computer Science, Hardware & Architecture, Engineering, Electrical & Electronic, Computer Science, Engineering

Abstract:

We present the fabrication process of a fully functional 0.274μm2 6T-SRAM cell with inserted-TaxNy Tall Tripple Gate devices. Several advancements over our previous report [1] are: Reduction of the 6T-SRAM cell size from 0.314 to 0.274μm2 using futher litho process optimizations Insertion of 5nm TaN-based layer in the gate stack of the cell devices Improved OPC for CD control and integration of SRAM and Logic A high static noise margin of 216mV at 1.0V has been achieved with devices having a Lg=37nm. This is the smallest 6T-SRAM cell with MG devices reported so far.