Symposium on VLSI Technology. Digest of Technical Papers, Date: 2005/06/14 - 2005/06/16, Location: Leuven Belgium
2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS
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Keywords:
Science & Technology, Technology, Computer Science, Hardware & Architecture, Engineering, Electrical & Electronic, Computer Science, Engineering
Abstract:
We present the fabrication process of a fully functional 0.274μm2 6T-SRAM cell with inserted-TaxNy Tall Tripple Gate devices. Several advancements over our previous report [1] are: Reduction of the 6T-SRAM cell size from 0.314 to 0.274μm2 using futher litho process optimizations Insertion of 5nm TaN-based layer in the gate stack of the cell devices Improved OPC for CD control and integration of SRAM and Logic A high static noise margin of 216mV at 1.0V has been achieved with devices having a Lg=37nm. This is the smallest 6T-SRAM cell with MG devices reported so far.