ESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference; 13-15 September 1999; Leuven, Belgium., Location: Leuven Belgium
Publication date:
1999-01-01
Volume:
13-15 Sept. 1999
Pages:
412 -
415
ISSN:
2863322451, 9782863322451
European Solid-State Device Research Conference
Author:
Kubicek, Stefan
Vandenberghe, Geert ; Schaekers, Marc ; Kol'dyaev, Victor ; Jansen, Philippe ; Badenes, Gonçal ; Deferm, Ludo ; De Meyer, Kristin ; Kerr, Daniel ; Naem, Abdalla
Abstract:
A 0.13 μm CMOS technology with the gate level written by Deep-UV Alternating Phase-Shift Mask and optimised polySi/NO- oxide gate stack is presented. Tradeoffs between NO-oxide vs. SiO2and B vs. BF2as junction dopants are analysed. The effects of various NO-oxides on NMOS and PMOS transistor characteristics are, clearly demonstrated and explained. Flat V.,=f(Lpo/y) characteristics with drive currents of 630 fJA/μm and 330 fJA/μm (off state currents less than 1 nA/μm) measured at a supply voltage of 1.5 V for NMOS and PMOS transistors, respectively, are achieved.