IEEE Journal of Solid-State Circuits vol:36 issue:6 pages:969-978
In this paper, the 0.35-mum implementation of a 1-Mb embedded flash memory circuit, based on a split-gate concept as described in , is presented. This concept provides an excellent solution for embedded applications, thanks to the very limited number of processing steps that are needed on top of a baseline CMOS process. Nevertheless, a highly performing memory cell is obtained that operates with moderate voltages only. Furthermore, the source-side injection (SSI) mechanism used for cell programming exhibits a very narrow threshold voltage (Vt) distribution, which is maintained even after 1 million program/erase cycles. Because of this tight distribution and the inherent overerase immunity, no additional verify circuitry is needed, which greatly simplifies the decoder design and minimizes the memory footprint. Finally, the memory cell is placed in a quasi-virtual ground array (QVGA) configuration, resulting in a compact memory area with only three quarters of a contact per cell, whereas most arrays require at least a full contact per cell or more.