Japanese journal of applied physics part 1-regular papers short notes & review papers vol:42 issue:4B pages:2020-2024
High-k insulators are currently considered for SiO2 replacement as gate dielectrics in sub-100nm complementary metal-oxide-semiconductor (CMOS) technology nodes. The use of double-layer high-k stacks as tunnel dielectrics could bring important benefits in the nonvolatile memory operation by either reducing the operating voltages and/or increasing the, programming speed. In this paper, the influence of the high-k parameters on the tunneling current and requirements for achieving higher programming speed without compromising retention are discussed. We show that enhancement of the tunneling current is possible with two-layer low-k/high-k dielectric stacks and confirm the theoretical results based on our experimental data.