IEEE Electron Device Letters vol:24 issue:2 pages:99-101
Low-voltage low-power nonvolatile floating-gate memory device operation can be achieved by using alternative tunnel barriers consisting of at least two dielectric layers with different dielectric constants kappa. Low-kappa/high-kappa (asymmetric) and low-kappa/high-kappa/low-kappa (symmetric) barriers enable steeper tunneling current-voltage characteristics. Their implementation is possible with high-kappa dielectric materials that are currently investigated for SiO2 replacement in sub-100-nm CMOS technologies. We show that a reduction in programming voltages of up to 50% can be achieved. This would significantly reduce the circuitry required to generate the high voltages on a nonvolatile memory chip, while maintaining sufficient performance and reliability.