Author:

Keywords:

Science & Technology, Technology, Engineering, Electrical & Electronic, Engineering, Approximate computing, ConvNet, convolutional neural network (CNN), deep learning, Dynamic-Voltage-Accuracy-Scaling, processor architecture, voltage scaling, 0204 Condensed Matter Physics, 0906 Electrical and Electronic Engineering, 1099 Other Technology, Electrical & Electronic Engineering, 4009 Electronics, sensors and digital hardware

Abstract:

© 2017 IEEE. A precision-scalable processor for low-power ConvNets or convolutional neural networks is implemented in a 40-nm CMOS technology. To minimize energy consumption while maintaining throughput, this paper is the first to implement dynamic precision and energy scaling and exploit the sparsity of convolutions in a dedicated processor architecture. The processor's 256 parallel processing units achieve a peak 102 GOPS running at 204 MHz and 1.1 V. It is fully C-programmable through a custom generated compiler and consumes 25-287 mW at 204 MHz and a scaling efficiency between 0.3 and 2.7 effective TOPS/W. It achieves 47 frames/s on the convolutional layers of the AlexNet benchmark, consuming only 76 mW. This system hereby outperforms the state-of-the-art up to five times in energy efficiency.