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Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 6, Date: 2016/01/01 - 2016/01/05, Location: San Diego, CA USA

Publication date: 2016-01-01
Volume: 72 Pages: 31 - 42
ISSN: 9781607685395
Publisher: Electrochemical Society

Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 6

Author:

Veloso, Anabela
Altamirano Sanchez, Efrain ; Brus, Stephan ; Chan, BT ; Cupak, Miroslav ; Dehan, Morin ; Delvaux, Christie ; Devriendt, Katia ; Eneman, Geert ; Ercken, Monique ; Huynh Bao, Trong ; Ivanov, Tsvetan ; Matagne, Philippe ; Merckling, Clement ; Paraschiv, Vasile ; Ramesh, Siva ; Rosseel, Erik ; Rynders, Luc ; Sibaja-Hernandez, Arturo ; Suhard, Samuel ; Tao, Zheng ; Vecchio, Emma ; Waldron, Niamh ; Yakimets, Dmitry ; De Meyer, Kristin ; Mocuta, Dan ; Collaert, Nadine ; Thean, Aaron

Keywords:

Science & Technology, Physical Sciences, Technology, Electrochemistry, Engineering, Electrical & Electronic, Materials Science, Multidisciplinary, Engineering, Materials Science, SILICON-NITRIDE, HIGH-DENSITY, 4008 Electrical engineering, 4017 Mechanical engineering, 4018 Nanotechnology

Abstract:

©The Electrochemical Society. This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral GAA-NWFETs, these devices are shown to have the potential for exhibiting lower parasitic RC and reduced power consumption at 5nm node design rules. They can also allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values. A comprehensive overview of some key integration aspects for VNWFET fabrication will also be addressed here, covering: VNW arrays, gate/top electrodes, and bottom/top isolation layers formation. In addition, we also present alternative solutions to obtain improved process control and to overcome etch-layout dependences which are especially critical within the context of vertical device integration using a channel-first approach.