Title: Radiation Hardened by Design, Low Jitter, 2.56 Gbps LVDS/SLVS Based Receiver in 65 nm CMOS
Authors: Faes, Bram
Christiansen, Jorgen
Rodrigues Simoes Moreira, Paulo
Reynaert, Patrick
Leroux, Paul
Issue Date: 28-Sep-2016
Conference: Topical Workshop on Electronics for Particle Physics (TWEPP) location:Karlsruhe, Germany date:26-30 September 2016
Article number: 43
Abstract: This paper proposes a 2.56 Gbps, radiation hardened by design, LVDS/SLVS like receiver designed in a commercial 65 nm CMOS technology. Simulation results predict 500 µW power consumption and 400 fs RMS output jitter. A replica receiver with a compensation loop is used to measure and compensate variations in the propagation delay of the output edges due to total ionizing dose (TID) radiation effects and/or process-temperature and voltage variations. This loop will ensure an equal propagation delay of the rising and falling output edges, to allow the use in accurate timing circuits.
Publication status: published
KU Leuven publication type: IMa
Appears in Collections:ESAT - MICAS, Microelectronics and Sensors
Technologiecluster ESAT Elektrotechnische Engineering
Electrical Engineering (ESAT) TC, Technology Campus Geel

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