Topical Workshop on Electronics for Particle Physics (TWEPP) location:Karlsruhe, Germany date:26-30 September 2016
This paper proposes a 2.56 Gbps, radiation hardened by design, LVDS/SLVS like receiver designed in a commercial 65 nm CMOS technology. Simulation results predict 500 µW power consumption and 400 fs RMS output jitter. A replica receiver with a compensation loop is used to measure and compensate variations in the propagation delay of the output edges due to total ionizing dose (TID) radiation effects and/or process-temperature and voltage variations. This loop will ensure an equal propagation delay of the rising and falling output edges, to allow the use in accurate timing circuits.