Semiconductor science and technology vol:16 issue:6 pages:427-432
A model for the tunnelling current through SiO2/ZrO2 gate dielectric stacks is presented, taking into account the trap-assisted tunnelling process through traps located below the conduction band of the ZrO2 layer. It is shown that the experimental results observed on n-Si/SiO2/ZrO2/Au capacitors at low voltage can only be reproduced with realistic values of the physical parameters when the trap-assisted contribution to the tunnelling current is included. The increase in the gate current density observed in a SiO2/ZrO2 gate stack during constant gate voltage stress was investigated next. It is shown that the stress-induced leakage current can also be very well explained by the trap-assisted tunnelling model, taking into account the increase in the trap density N-t with stress time. It is found that N-t, varies as a power law with the stress time in the ZrO2 layer, as in ultra-thin thermal SiO2 layers. It is suggested that the same degradation mechanism could occur in these different materials, namely H+ generation and transport through the gate dielectric during the electrical stress, resulting in bond breaking and neutral trap generation.