Design strategy for integrating DSA via patterning in sub-7 nm interconnects
Karageorgos, Ioannis × Ryckaert, Julien Tung, Maryann C Wong, Philip H -S Gronheid, Roel Bekaert, Joost Karageorgos, Evangelos Croes, Kris Vandenberghe, Geert Stucchi, Michele Dehaene, Wim #
SPIE Digital Library
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X pages:97810N-97810N-9
SPIE Advanced Lithography edition:9781 location:San Jose, California, United States date:21-25 February 2016
In recent years, major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCPs). As a result, the insertion of DSA for IC fabrication is being actively considered for the sub-7 nm nodes. At these nodes the DSA technology could alleviate costs for multiple patterning and limit the number of lithography masks that would be required per metal layer. One of the most straightforward approaches for DSA implementation would be for via patterning through templated DSA, where via hole patterns are readily produced through templated confinement of cylindrical phase BCP materials.
Our in-house studies show that decomposition of via layers in realistic circuits below the 7 nm node would require at least many multi-patterning steps (or colors), using 193 nm immersion lithography. Even the use of EUV might require double patterning in these dimensions, since the minimum via distance would be smaller than EUV resolution. The grouping of vias through templated DSA can resolve local conflicts in high density areas. This way the number of required colors can be significantly reduced.
To implement this approach, a DSA-aware mask decomposition is required. In this paper, a design method for DSA via patterning in sub-7 nm nodes is discussed. We present options to expand the list of DSA-compatible via patterns (DSA letters). Additionally, we define cost formulas and we develop a tool for the optimal DSA-aware layout decomposition.