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Title: Design and simulation of on-chip circuits for parallel characterization of ultrascaled transistors for BTI reliability
Authors: Putcha, Vamsi
Groeseneken, Guido
Issue Date: Oct-2014
Host Document: pages:99-102
Conference: Integrated Reliability Workshop Final Report (IIRW), 2014 IEEE International location:South Lake Tahoe, CA date:12-16 Oct. 2014
Abstract: A novel on-chip test circuit architecture to perform BTI
characterization of single devices using the Measure-Stress- Measure (MSM) method is designed and simulations were performed to confirm that the design is fully functional. Characterization throughput was maximized using pipelining. A ‘place-and-check’ algorithm was developed to generate optimized pipelining of individual device measurements. The novel pipelining methodology was corroborated with real measurements, in accordance with the generated pipelining sequence and proposed circuit architecture. The results are shown to be consistent with the data obtained from conventional measurement methods and an improvement of 82% was achieved in total BTI characterization time of 4096 devices.
Publication status: published
KU Leuven publication type: IC
Appears in Collections:ESAT - MICAS, Microelectronics and Sensors

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