Author:

Keywords:

DSA, templated via, block copolymer, 7nm, grapho-epitaxy, primary cluster pattern, checkerboard grid, VIA cluster, Science & Technology, Physical Sciences, Technology, Optics, Physics, Applied, Imaging Science & Photographic Technology, Physics, Directed Self-Assembly, templated DSA flow, implementation, via patterning, cylinder phase block copolymer, 4006 Communications engineering, 4009 Electronics, sensors and digital hardware, 5102 Atomic, molecular and optical physics

Abstract:

In recent years major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCP). Insertion of DSA for IC fabrication is seriously considered for the 7nm node. At this node the DSA technology could alleviate costs for double patterning and limit the number of masks that would be required per layer. At imec multiple approaches for inserting DSA into the 7nm node are considered. One of the most straightforward approaches for implementation would be for via patterning through templated DSA (grapho-epitaxy), since hole patterns are readily accessible through templated hole patterning of cylindrical phase BCP materials. Here, the pre-pattern template is first patterned into a spin-on hardmask stack. After optimizing the surface properties of the template the desired hole patterns can be obtained by the BCP DSA process. For implementation of this approach to be implemented for 7nm node via patterning, not only the appropriate process flow needs to be available, but also appropriate metrology (including for pattern placement accuracy) and DSA-aware mask decomposition are required. In this paper the imec approach for 7nm node via patterning will be discussed.