Author:

Abstract:

The pace of evolution of embedded applications, such as wireless communication, multimedia, etc., has been challenging system designers on multiple aspects. These systems are expected to continuously push boundaries in terms of energy efficiency, performance, cost and supported functionality. For example, modern day smartphone systems are expected to deliver a performance of 100 GOPS in a power budget of less than 1W. This has led to the emergence of complex heterogeneous multi-processor System-on-Chip (MPSoC) based platforms. Design and implementation of these MPSoC platforms is nontrivial, given the exponentially increasing design space they present, in terms of application, architecture and technology choices. Moreover, in deep-submicron technology nodes, it has become inevitable to directly include the strong impact of the technology on the architecture choices. Thus, not only a systematic exploration approach but also a close coupling of different phases of system design, starting from high-level algorithm design to low-level physical design, has become unavoidable. It will allow understanding and analysis of implications of design choices across different design phases, in the face of increasing complexity of applications and architectures, and the increasing uncertainty in the underlying technology. The motivation for this thesis is to bridge the application, system-level architecture and technology design aspects for mitigating the system design challenges in terms of design space complexity, design efficiency, cost, technology scaling, battery gap and memory wall. Towards the application-architecture codesign, the thesis proposes a systematic methodology for application mapping and architecture exploration. The proposed methodology enables an early exploration of the partitioning and assignment search space of the streaming multi-mode applications “together” with the available platform architecture topology choices. The proposed methodology also systematically explores instantiation of a template-based domain-specific MPSoC platform architecture, which results in better than worst-case energy efficiency for platform instantiation to support multi-mode applications. Further, the thesis explores the architecture and interconnect technology implications of fine-grained 3D partitioning for complex MPSoC platforms instantiated for streaming multi-mode applications. The thesis presents a design framework that extends the above methodology to carry out 2D versus 3D integration evaluations and comparisons. Multiple 3D stacked integrated circuit (3D-SIC) alternatives, (a) TSVs/RDL/µbump based (Face-to-Back, F2B) and (b) Cu-Cu bonding based (Face-to-Face, F2F), are considered and their suitability and impact on system level design for such complex MPSoC platforms are analyzed. The thesis also carries out a systematic analysis of different system level architectures and the variation in their impact on 2D and F2F 3D-SIC integration technologies, and vice versa. As a part of the thesis, an architecture template for a low power processor for wireless baseband processing, called BoT, has also been implemented. All the above mentioned work has been carried out using the BoT and it is now also a part of the commercial offering under the Green Radio program at Imec.