Title: Bias Temperature Instability in CMOS Digital Circuits from Planar toFinFET Nodes
Other Titles: Bias Temperatuur Instabiliteit (BTI) in digitale CMOS schakelingen vanvlakke naar FinFETtransistortechnologie
Authors: Kükner, Selahaddin Halil; R0268623
Issue Date: 2-Apr-2015
Abstract: Reliability of electronic circuits has become one of the most prominent grand challenge in the near-term (2013-2020) and long-term (2021-2028) technology roadmap for the semiconductor industry. The CMOS scaling trends has resulted in deeply scaled device dimensions. In addition, the slow paced scaling of supply voltages in the decananometer CMOS era, has exacerbated stress levels on semiconductor ICs. Today, atomic scale device dimensions are triggering the discretisation/quantization of the reliability effects, e.g. although a decananometer CMOS device only consists few oxide traps, each single trap excitation or emission directly impacts a device’s threshold voltage shift. As a consequence, the scale of intrinsic parameter fluctuations in modern day devices are becoming increasingly unpredictable at the system level. For example, the reliability effects are highly workload-dependent, i.e. no more averaging, where the time constants are ranging from picoseconds to days. Last but not least, the nature of CMOS/beyond-CMOS scaling (towards the edge of the matter) will introduce new stimulating challenges and fundamental barriers for reliability, i.e. lithography, process control, new materials and device topologies, novel applications, more demanding mission profiles, etc. In conclusion, it is getting harder to counteract the reliability issue by only guard-banding or over-margined designs, which diminish the benefits of CMOS scaling.
To tackle the above challenges, this thesis targets the reliability modeling of the Bias Temperature Instability phenomenon in CMOS digital circuits, while covering the scaling impacts from planar to advanced FinFET process technology nodes. The first key contribution of this thesis is to propagate the BTI modeling from device to processor data-path and local memory level. The purpose is to analyze the impacts of the BTI degradation from the physical device level up to the block level to investigate the severeness of the BTI threat in CMOS digital circuits. This thesis also contributes by proposing fast and still accurate simulation frameworks at various design levels. The last key contribution of this thesis is to provide BTI-aware design guidelines at the device, gate and block level. The purpose is to support the CMOS digital circuit designers by providing design-time guidelines that enhance the lifetime and reliability of digital ICs against the BTI phenomenon.
Table of Contents: 1. Introduction
2. Time-Zero and Time-Dependent Variability
3. Bias Temperature Instability Models
4. Scaling of BTI from Planar FET to Advanced 3-D FinFET Nodes
5. BTI Degradation of Logic Gates with the Trap-based Model
6. Gate-level Comparison of BTI Models
7. BTI Aging on Datapath Logic Blocks from Planar to Advanced FinFET Nodes
8. Conclusions and Future Work
Publication status: published
KU Leuven publication type: TH
Appears in Collections:Associated Section of ESAT - INSYS, Integrated Systems
ESAT- TELEMIC, Telecommunications and Microwaves

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