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IEEE Transactions on Electron Devices

Publication date: 2014-01-01
Volume: 61 Pages: 2633 - 2639
Publisher: Institute of Electrical and Electronics Engineers

Author:

Nazir, Aftab
Spessot, Alessio ; Eyben, Pierre ; Clarysse, Trudo ; Ritzenthaler, Romain ; Schram, Tom ; Vandervorst, Wilfried

Keywords:

Science & Technology, Technology, Physical Sciences, Engineering, Electrical & Electronic, Physics, Applied, Engineering, Physics, 2-D carriers, modeling, MOSFETs, process/device simulation, scanning spreading resistance microscopy (SSRM), technology computer-aided design (TCAD), SPREADING RESISTANCE MICROSCOPY, RESOLUTION, 0906 Electrical and Electronic Engineering, Applied Physics, 4009 Electronics, sensors and digital hardware

Abstract:

In this paper, we illustrate how high-resolution 2-D carrier profiles from scanning spreading resistance microscopy (SSRM) can be used to predict and understand device performance of dynamic random access memory peripheral transistors with high-k metal gate and ultrashallow junctions. In an earlier study on high-speed complementary metal-oxide-semiconductor logic, the 2-D carrier profiles from SSRM were used as the active 2-D dopant profile input to the device simulator as they are virtually identical. The extensive mobile carrier diffusion caused by the lower concentrations, however, implies a strong difference between the mobile carrier distribution and the dopant distribution such that the same approach is no longer valid. Ideally one would have to generate, based on the carrier profiles, the active dopant distribution through the inverse solution of the Poisson equation (in two dimensions) which is, however, numerically nontrivial and often leads to nonunique results. Therefore, an alternative approach is proposed here, whereby we fine-tune the process simulations such that the resulting simulated carrier profiles match the 2-D SSRM profiles. Upon reaching satisfactory agreement, the simulated profiles can be used as input for a device simulator and be used to predict sensitive device parameters such as drain-induced barrier lowering and threshold voltage rolloff. © 2014 IEEE.