In the near future, Tb/s-class aggregate bandwidth input/output (I/O) circuits will be needed for high-end performance computing systems. A high-performance I/O using optical transmission technology is being considered to overcome the limitation of a conventional electrical I/O in terms of data rate per channel, a bandwidth per millimeter and power consumption. A silicon photonics technology is very promising candidate to realized Tb/s-class aggregate I/O bandwidth with improved energy efficiency targeting cost-effective short-range optical links. The main focus in this work is put on CMOS circuitry design to enable low power and high speed optical link between two packages. On the transmitter side of the optical link, energy efficient CMOS driver circuit was co-designed with silicon ring modulator to maximize optical modulation amplitude and to reduce insertion loss. The receiver circuit, designed as a chain of inverted-based stages allows to amplify and convert current pluses detected by a germanium photodiode to usable voltage. The models of the key silicon photonics devices: ring modulator and germanium photodiode allowed to improve the CMOS circuit design targeting the highest energy efficiency. The models of the optical active devices as well as grating couplers, silicon waveguide and fibers were implemented in Verilog-A allowing co-simulation with the CMOS circuits. Thanks to that the complete CMOS silicon photonics link was simulated in a single environment. To demonstrate optical transmission silicon photonics die was integrated with co designed CMOS chip by a standard flip-chip technique. The silicon photonics chip containing optical active and passive devices was fabricated in imecs 200mm pilot line using a subset of 130nm CMOS processing modules. The demonstrator allow to transmit and received data via optical link at 10Gb/s and 20Gb/s. Measured power consumption on the complete optical transceiver showed very good agreement when compared with the simulations results.