Integration of radios into low cost CMOS technology enables widespread usage of mobile devices. However, despite the general success in CMOS radio development, realization of efficiency CMOS power amplifiers remains a persisting challenge. This is because of both the stringent requirements of the modern wireless standards and the drawbacks of the CMOS technology for RF power amplification.Modern wireless standards targets higher and higher data rates. Thus, they utilize high order modulation schemes and wide bandwidth. Therefore, they require wideband linear power amplifiers with high back-off efficiency. In addition, the modern radios should be very flexible in terms of output power to optimize both the battery life and communication capacity.To address these issues, we proposed transformer-based Doherty topology. This topology offers high efficiency for a wide power range without the need of additional supply voltage or external components. The proposed architecture uses complexity to overcome linearity efficiency trade-off. The proposed amplifier combines several amplifiers with different gain characteristics. The number of combined amplifiers is adjusted depending on the required power level. The power combining is anyhow necessary in nanoscale CMOS technology in order to achieve the required power levels with low voltage transistors. In this topology, the power combining is used to further enhance the linearity and efficiency. Therefore, the proposed topology does not bring area or cost overhead compared to conventional linear PAs.The analysis of the proposed architecture is presented in chapter 3 in comparison with the other LC based and transformer-based CMOS power amplifiers. The optimum design parameters are calculated. To validate the performance of the proposed topology, we fabricated five chips in standard CMOS technology: The uneven Doherty WLAN PA that is fabricated in 90 nm CMOS technology satisfies the stringent EVM and spectral mask requirements of the WLAN standard at 20.2 dBm output power level with a PAE of 24.7 %. This high efficiency under WLAN signal proves the linearization and back-off efficiency enhancement behavior of the proposed architecture.The dual mode Doherty LTE PA that is fabricated in 40 nm CMOS technology satisfies the stringent EVM and spectral mask requirements of the LTE standard at 23.4 dBm output power with a PAE of 23.3 %. When the transmitter requires 6 dB (12 dB) lower output power the PAE is still as high as 18.4 % (11.1 %). The PA demonstrates high efficiency especially at back-off levels. The PAE at 12 dB back-off level is 2 times higher than the previously demonstrated fully integrated CMOS PAs. This behavior significantly improves the battery life because the PA often operates at back-off.The proposed transformer based Doherty topology is also demonstrated at mm-wave frequencies. The E-band Doherty PA that is fabricated in 40 nm CMOS technology achieves a saturated output power of 16.2 dBm with a peak PAE of 12 %. The output referred 1dB compression point is 15.2 dBm and the PAE at 1 dB compression point is 11.1 %. In addition, the PAE at 6 dB back-off is still as high as 5.7 %. Furthermore, the proposed topology does not bring area overhead. The core area of the E-band Doherty PA is only 0.1 mm2 . Therefore, transformer-based Doherty topology can be used to replace the conventional amplifiers in the mm-wave transmitters to increase the energy efficiency.