Title: Hybrid hexagonal/classical tiling for GPUs
Authors: Grosser, Tobias
Cohen, Albert
Holewinski, Justin
Sadayappan, P.
Verdoolaege, Sven
Issue Date: Feb-2014
Publisher: ACM
Host Document: Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization pages:66-75
Conference: International Symposium on Code Generation and Optimization location:Orlando, Florida date:15-19 February, 2014
Abstract: Time-tiling is necessary for the efficient execution of iterative
stencil computations. Classical hyper-rectangular tiles cannot be
used due to the combination of backward and forward dependences
along space dimensions. Existing techniques trade temporal data
reuse for inefficiencies in other areas, such as load imbalance,
redundant computations, or increased control flow overhead,
therefore making it challenging for use with GPUs.

We propose a time-tiling method for iterative stencil computations
on GPUs. Our method does not involve redundant computations. It
favors coalesced global-memory accesses, data reuse in
local/shared-memory or cache, avoidance of thread divergence, and
concurrency, combining hexagonal tile shapes along the time and one
spatial dimension with classical tiling along the other spatial
dimensions. Hexagonal tiles expose multi-level parallelism as well
as data reuse. Experimental results demonstrate significant
performance improvements over existing stencil compilers.
Publication status: published
KU Leuven publication type: IC
Appears in Collections:Informatics Section

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