Author:

Keywords:

Organic, Ferroelectric, Memory, Thin-film, Transistor, P(VDF-TrFE), Semiconductor

Abstract:

In recent years, organic thin-film electronics have emerged as a route towards flexible, low-cost, large area applications, which are unfeasible in the current silicon technology. For example, low-cost radio frequency identification (RFID) tags that can be placed on any object, as envisioned by the ’Internet of Things’, for smart labeling, security, monitoring, or tracking purposes. For these applications, a nonvolatile memory functionality is crucial for their intended operation. Therefore, simultaneous to the development of organic transistors and circuits, progress needs to be made towards a compatible nonvolatile, electrically reprogrammable memory array. In this doctoral research, we aim to realize such an organic memory array that can be integrated with the organic logic circuits on the same, flexible substrate. More specifically, we focus on the device architecture and materials of ferroelectric field-effect transistors (FeFET) as the basic memory unit. The objective of this work was pursued by a combination of i) technological advancements over the state-of-the-art; ii) further understanding of the device operation; iii) devising a read-and write scheme suited for an array; and iv) use of novel materials and device architectures. By optimizing the processing conditions, we demonstrate high-performance bottom gate - top contact (BG-TC) FeFETs with pentacene as the organic semiconductor, as shown in Chapter 2. These memory devices can switch within a few ms, and can be cycled for at least 10000 times. In addition, we experimentally demonstrate a long term retention data of more than one year. These results make this device highly promising for non-volatile memory applications. Unexpectedly for a bi-stable material, the BG-TC FeFET shows three reprogrammable memory states: ’OFF’, ’Intermediate’ and ’ON’ state. Using Scanning Kelvin Probe Microscopy, we elucidate the device operation in this device structure in Chapter 3. These measurements show that the ferroelectric layer in the channel region of the FeFET is not fully polarized in the ’OFF’ and ’Intermediate’ states. The difference between these two states can be explained by a different injection property of the contacts, caused by the ferroelectric polarization state underneath the source-drain contacts. This refinement clarifies the peculiarities experimentally found in literature, as well as in our own results. To integrate with organic circuits, as well as to fabricate memory arrays, photolithography must be used. In addition, the bottom gate - bottom contact (BG-BC) device architecture needs to be adopted. By further technology development, we realize such a memory FeFET that can be integrated with current state-of-the-art organic circuits on flexible substrates, as demonstrated in Chapter 4. Moreover, we employ this technology to fabricate a passive NAND array, as described in Chapter 5. The NAND architecture was chosen, as it offers the highest possible density of all transistor memory arrays. Despite the fact that passive arrays are more challenging to reliably address all FeFETs, we demonstrate a non-destructive read and write operation in the NAND array. Finally, novel device architecture and materials are explored to improve the memory characteristics in Chapter 6. Replacing pentacene with novel, high mobility semiconductors alone are proven to be unsuccessful to enlarge the memory window in the BG-BC FeFET. On the other hand, by adapting a planar heterojunction structure in the device, the memory window can be significantly enlarged by 30-60 %. The heterojunction device architecture is promising for further improvements, as many combinations of organic semiconducting materials are possible.