Title: Reconfigurable All-Digital Time-To-Digital Converter for Digital PLL (Configureerbare volledig digitaal tijd-naar-digitaal convertor voor digitaal PLL)
Other Titles: Reconfigurable All-Digital Time-To-Digital Converter for Digital PLL
Authors: Vengattaramane, Kameswaran; S0183840
Issue Date: 17-Feb-2014
Abstract: This PhD work focuses on Time‐to‐Digital Converters (TDC) for frequency synthesis insoftware‐defined radios (SDR). Specifically, it addresses the resolution enhancementof TDC with low‐complexity digital post‐processing and calibration. TDCs are used asphase‐difference detectors in digital‐intensive phase‐locked loops (DPLL). Such PLLsare promising, as they are not impacted by the analog “unfriendliness” of deepsubmicronCMOS. However, the performance as characterized by in‐band noise of the synthesized carrier depends strongly on the resolution of the TDC used.The available basic TDC resolution is the delay of a loaded inverter in any technology.In literature, there are several circuit/system approaches to go below the gate delay,with the incurred power penalty. Such techniques are analog‐intensive, not easilyported across different technologies and run contrary to the ‘go‐digital’ philosophyof the DPLL. Further, these techniques provide a fixed resolution TDC. In an SDR,block‐level power‐performance knobs are desirable to enable power optimizationbased on quality‐of‐service demand. Thus there is a need for TDC architectures thatnot only achieve sub‐gate delay resolutions, but also have resolutionreconfigurability. They should migrate easily with the process technology evolutionmeaning that digital‐domain techniques are preferred over custom analogtechniques. Also, from a functional simulation point‐of‐view, digital–domainimplementations are preferred, as they result in faster system verification and canmake use of the vast strides made in EDA tools for system development.In this work, the concept of Spatially Oversampled TDC System is presented, wherethe resolution enhancement over a gate delay is obtained by low‐complexity digitalpost‐processing of several parallel TDC outputs. These parallel TDCs have slightlydifferent resolutions and measure the same input. The simultaneous sampling of theinput with different resolution TDCs when combined, results in an oversampledquantization grid with a plurality of sampling edges. Knowing the individual TDCresolutions, multiple coarse time‐interval estimates can be derived. These estimatesare then arithmetically processed using metrics like maximum, minimum, andaverage to result in a final estimate with much better precision and accuracy thanany individual TDC used in the parallel system. This system emulates a fineresolution TDC using only digital‐domain techniques. The achieved resolutionenhancement depends on the number of channels (TDCs) used and hence resolutionreconfigurability is readily incorporated.Two test prototypes are realized on silicon using 90 nm CMOS technology. In the firstprototype, a system with 8 parallel current starved ring oscillator based TDCs isdesigned. The resolution of coarse TDCs is changed by setting the current drivethrough a programmable word. Measurements show a 3X improvement over abuffer delay [52‐62] ps validating the system principle. In the second prototype, afully digital standard‐cell based 8 channel TDC architecture is developed. Itincorporates an online background calibration scheme to track the individual TDCresolutions and is a fully integrated implementation with all the post‐processingdone on‐chip. The measured effective resolution is [14‐40] ps. These two prototypesdemonstrate the viability of the fully digital alternative for resolution enhancementin TDCs.
Publication status: published
KU Leuven publication type: TH
Appears in Collections:ESAT - MICAS, Microelectronics and Sensors
Electrical Engineering - miscellaneous

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