Analysis and Implementation of Hardware Techniques for Low-Energy Instruction Memory Organisations in Embedded Systems (Analyse en realisatie van hardwaretechnieken voor laagvermogen instructiegeheugens in ingebedde systemen)
Analysis and Implementation of Hardware Techniques for Low-Energy Instruction Memory Organisations in Embedded Systems
Artés García, Antonio; R0438054
The design of current embedded systems is constrained by the requirements of modern embedded applications. Many of these applications require not only sustained operation for long periods of time, but also to be executed on battery powered systems. Under the constraint of not being mains-connected, the absence of wires to supply a constant source of energy causes that the use of an energy harvesting source or an integrated energy supplier limits the operation time of these electronic devices. Instruction memory organisations are pointed out as one of the major sources of energy consumption in embedded systems. As these systems are characterised by restrictive resources and a low-energy budget, any enhancement that is introduced in the instruction memory organisation allows not only to decrease the energy consumption, but also to have a better distribution of the energy budget throughout the embedded system. This Ph.D. thesis focuses on the study, analysis, proposal, implementation, and evaluation of low-energy optimisation techniques that can be used in the instruction memory organisations of embedded systems. Real-life embedded applications of the specific subdomain of wireless sensor nodes are used as benchmarks to show, analyse, and corroborate the benefits and disadvantages of each one of the concepts in which this Ph.D. thesis is based on. The first key contribution is the systematic study of existing low-energy optimisation techniques that are used in instruction memory organisations, outlining their comparative advantages, drawbacks, and trade-offs. On top of that, the experimental evaluation that is presented in this Ph.D. thesis uses a systematic method in order to have an accurate estimation of parasitics and switching activity. Due to this fact, this evaluation guides embedded systems designers to make the correct decision in the trade-offs that exist between energy budget, required performance, and area cost of the embedded system. The second key contribution is the development of a high-level energy estimation tool that, for a given application and compiler, allows the exploration not only of architectural and compiler configurations, but also of code transformations that are related to the instruction memory organisation. The third key contribution is the proposal and analysis of several promising implementations of energy-efficient instruction memory organisations for a specific set of application codes and embedded architectures. Based on the previous contributions, the work that is presented in this Ph.D. thesis proves why further optimising instruction memory organisations from the energy consumption point of view will remain an extremely important trend in the future.