Title: Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission (Continue-tijd digitale front-ends voor multistandaard draadloze transmissie)
Other Titles: Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission
Authors: Nuyts, Pieter; S0107108
Issue Date: 11-Jun-2013
Abstract: Modern wireless devices often have to support multiple communication standards while keeping their power consumption and physical size low. This leads to the tendency to implement as many parts as possible using digital rather than analog hardware, since it can more easily be reconfigured to support multiple standards. Furthermore, digital hardware can easily be integrated in standard CMOS chips and benefits more from technology scaling.As CMOS technology advances, the allowable supply voltage decreases. Because of this, achieving good voltage linearity becomes a major problem. This degrades the performance of analog circuits, while digital circuits remain largely unaffected. Just like digital circuits, switched-mode power amplifiers (SMPAs) use only two voltage levels and therefore do not depend on voltage linearity. Furthermore, they are more efficient than linear power amplifiers and they can be driven directly by digital signals, which makes them the ideal choice for implementing multistandard digital transmitters in standard CMOS.However, SMPAs are not suitable to amplify amplitude-modulated signals, so that both the phase and the amplitude information must be encoded in the time domain. Since modern communication standards use very demanding modulation schemes, this requires very good time resolution. While the resolution of clocked digital circuits is limited to the sampling period, which is typically several hundreds of picoseconds, continuous-time digital circuits can achieve much better resolutions - in the order of 1 to 10 ps - by using gate delays rather than clock periods as the minimal time unit. This allows a maximal shift of information from the voltage to the time domain, where resolution keeps improving thanks to the increasing transistor speeds.This work investigates the design of continuous-time digital multistandard transmitter front-ends for carrier frequencies ranging from 900 MHz to 3 GHz, where the complete transmitter chain up to the power amplifier input is based on digital gates. Different architectures are investigated, which leads to the choice for polar continuous-time digital transmitters based on pulse width modulation (PWM). The effect of PWM and digitization of the signals is investigated using mathematical models and high-level Matlab simulations. Next, the focus is moved to the circuit level, where the fundamentals of continuous-time digital design are addressed. The presented research is validated using two test chips implemented in 65-nm and 40-nm CMOS. Measurement results for both chips demonstrate the feasibility of fully digital CMOS RF transmitters, and furthermore they confirm the derived high-level models and the beneficial effect of technology scaling on this type of circuits.
Table of Contents: 1. Introduction
2. Digital Transmitter Architectures: Overview
3. High-Level Analysis of Fully Digital PWM Transmitters
4. Continuous-time Digital Design Techniques
5. A 65-nm CMOS Fully Digital Reconfigurable Transmitter Front-End for Class-E PA based on Baseband PWM
6. A 40-nm CMOS Fully Digital Reconfigurable Transmitter with Class-D PAs using Baseband and RF PWM
7. Conclusions and Future Work

A. Definitions, Conventions and Overview of Used Theory
B. Derivations and Considerations Regarding PWM
ISBN: 978-94-6018-671-4
Publication status: published
KU Leuven publication type: TH
Appears in Collections:ESAT - MICAS, Microelectronics and Sensors

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