Author:

Abstract:

In this experimental work, the capacitance-voltage (CV) and ac conductance-voltage (GV) methods of electrical characterization have been combined with electron spin resonance (ESR) analysis to study charge properties and distribution of traps at interfaces of both traditional silicon and high-mobility semiconductors such as SiGe, Ge, and III-V compound semiconductors. The studied insulators range from thermal SiO2 to its counterparts of high dielectric constant (k) such as HfO2 and TaSiOx. Extension of the electrical characterization to low temperatures enabled to obtain results of enhanced reliability by suppressing the minority carrier response and thermal emission of charge carriers from interface traps. A first part of the work is focused on an in-depth analysisof the interface trap density, Dit, in (110)Si/SiO2 in comparison with the well studied (100) and (111)Si/SiO2 interfaces. It is found that Ditis highly sensitive to the Si face orientation, the highest density encountered at the (111) face, the lowest at the (100) face, with the (110)Si/SiO2 interface closely resembling the (111)Si/SiO2 case. Two peaks inthe Dit-vesus-energy profile within Si band gap are observed for all three orientations, which appear to be strongly correlated with the presence of paramagnetic interfacial Pb(0) defects, i.e., Si dangling bonds (DBs), responsible for the majority of interface charge traps. By comparing CV curves at 300 K and 77 K measured both on p-and n-type samples, we affirmed the amphoteric properties of the traps at all three Si/SiO2 interfaces. Whereas the atomic nature and the energy distribution of the traps at the studied interfaces appear very similar, comparison between the areal densities of the Si Pb0-centers and (110)Si/SiO2 interface trapsreveals that not all Pb0s are operating as charge traps. We suggest clustering of the interfacial Si DB defects as the possible mechanism of electrical inactivation of part of the Pb0 centers at the interface. In the second part, it is found that low temperature (77 K) CV measurements can be used as an adequate method to extract charge trap properties in c-Si/a-Si:H structures. Combined with ESR analysis, the experiments on (100)Si/intrinsic a-Si:H reveal the presence of electrically active Pb0 defects at the interface as well as D-centers distributed throughout the a-Si layer, detected both by electrical and ESR techniques in similar densities. The significance of this work lies with the atomic identification of defects in this stack, coupled with their electrical activity. A next topic deals with the full cycle investigation of thekinetics of hydrogen passivation and depassivation of Ge DBs at Si0.25Ge0.75/SiO2 interfaces grown by the condensation method. It is found thatthe passivation of the Ge DB defects (GePb1 centers) occurs similarly to the case of SiPb defects, with the mechanisms of defect-hydrogen interaction being well described by the generalized simple thermal model. Theobtained activation energies for the GePb1 system are somewhat smaller than those in the case of interfacial Si DBs (Pb-type centers at Si/SiO2interfaces). However, as a key finding, the values of spreads in activation energies are much higher than those obtained for SiPbs in Si/SiO2 entities. In sharp contrast with SiPbs, the GePb1 centers cannot be passivated efficiently in molecular H2 to device-grade level for thermal budgets up to 400 oC, with only ~60 % inactivation obtained. This is a direct consequence of the excessive spreads in activation energies for the passivation and dissociation processes, related with the specific interface morphology. Next, we demonstrated that the passivation method by using an interlayer such as Si/SiO2 or Ge3N4 is a prospective way to improve electrical properties of Ge interfaces. In the case of passivation by a Si/SiO2 interlayer, we have demonstrated that a Si passivation layer grown using silcore at 350 oC shows a lower interface trap density in Ge/HfO2 structures than the passivation using Si grown from silane at a higher temperature (500 oC). In n-Ge/metal contacts, passivation by a plasma-grown Ge3N4 interlayer allows for solvingthe problem of Fermi level pinning on n-type Ge. Both amorphous and epitaxial Ge3N4 effectively unpin the Fermi level, resulting in a linear dependence of the metal/semiconductor barrier height on the metal work function.