Title: Novel self-aligned Ti silicide process for scaled CMOS technologies with low sheet resistance at 0.06-mu m gate lengths
Authors: Kittl, Jorge ×
Hong, QZ
Rodder, M
Breedijk, T #
Issue Date: May-1998
Publisher: Institute of Electrical and Electronics Engineers
Series Title: IEEE Electron Device Letters vol:19 issue:5 pages:151-153
ISSN: 0741-3106
Publication status: published
KU Leuven publication type: IT
Appears in Collections:Non-KU Leuven Association publications
× corresponding author
# (joint) last author

Files in This Item:

There are no files associated with this item.

Request a copy


All items in Lirias are protected by copyright, with all rights reserved.

© Web of science