Author:

Keywords:

Reliability, CMOS, Logic devices, (Si)Ge

Abstract:

Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled EOT down to 5Å, a 10 year device lifetime at operating voltage cannot be guaranteed anymore due to severe Negative Bias Temperature Instability (NBTI). Meanwhile, the use of high-mobility channels is being considered for next CMOS technology nodes. The (Si)Ge channel quantum well (QW) pMOS technology in particular offers enhanced mobility and threshold voltage tuning. This study focuses on the reliability of this novel technology. We observe that it also offers a remarkable reliability improvement. In particular, a significantly reduced NBTI is observed by optimizing the (Si)Ge gate stack with a high Ge fraction in the channel, a sufficiently thick QW and a Si passivation layer of reduced thickness. By means of such optimization, sufficiently reliable ultra-thin EOT SiGe pMOSFETs with a 10 years lifetime at operating conditions are demonstrated in both gate-first and gate-last process flows. Furthermore, the reliability improvement is observed to be process- and architecture-independent, proving to be an intrinsic property of the studied MOS system consisting of a Ge-based channel and a SiO2/HfO2 dielectric stack. We ascribe this superior reliability mainly to a reduced interaction between channel inversion holes and dielectric defects, thanks to a favorable energy alignment of the Fermi level in the (Si)Ge channel. Furthermore, we observe that this beneficial effect considerably alleviates also the time-dependent variability which arises as devices scale toward atomistic dimensions. Other reliability mechanisms are also investigated. While Hot Carrier degradation is identified as a possible threat for pure Ge channel pMOS devices, it is observed not to jeopardize the reliability of the NBTI-optimized SiGe gate stack. No significant difference with respect to standard Si channel technology is found for Time Dependent Dielectric Breakdown, while a reduced low-frequency noise is observed for optimized SiGe devices, consistently with the observation of reduced NBTI.The extensive experimental results here reported strongly support (Si)Ge technology as a clear frontrunner for future CMOS technology nodes, offering a solution to the reliability issues for ultra-thin EOT nanoscale devices.