Advanced Front-Side Technology in Crystalline Silicon Solar Cells (Geavanceerde Frontend-Side Technolgy in kristallijn silicium zonnecellen)
Advanced Front-Side Technology in Crystalline Silicon Solar Cells
Prajapati, Victor; S0203739
The goal of this thesis is to improve the efficiency of silicon solar cells such that the cost/watt could be reduced to a competitive level. In this thesis, three aspects of the front-side of crystalline silicon solar cells have been investigated. Advanced texturing, emitter formation and passivation are detailed in chapters 2, 3 and 4 respectively. Below, each chapter is summarized. In chapter 2, a new technique has been developed that textures the frontside while polishing the rear-side. The technique involves the application of an acrylic adhesive micro-masking layer to a rough, as-cut wafer. Upon removal, remnants of the adhesive layer adhere only to the peaks of the as-cut wafer. The wafer is then subject to a 4 minute 12.5 wt% heated NaOH etch, where the front-side of the wafer is textured and the rearside of the wafer is polished. The developed technique can lead to savings by: decreasing cycle time (4 min vs. 20 min conventional texturing time), saving consumables (one chemical solution vs. two) and reducing the amount of silicon loss (15 μm vs. 25 μm from texturing both sides and then polishing the rear). Equivalent solar cell efficiencies have been achieved when comparing the developed technique to conventional random pyramid textured and in-line polished wafers.Chapter 3 focuses on a novel emitter formation process that has been developed. The process involves the combination of ion implantation, passivation and annealing in a firing furnace. The developed process may enable ion implant technology to have a lower cycle time than conventional diffusion as the anneal is done in a firing furnace (within 90 seconds). Cell results show that implantation-induced damage can be annealed to an extent to reach open circuit voltages above 640 mV. Along with emitter formation, intentional and unintentional emitter alterations have also been investigated. wo processes that cause unintentional emitter etch back have been investigated, the rear emitter removal process as well as surface cleaning processes. Processes that alter the emitter profile necessitate an increase in sheet resistance monitoring. To reduce recombination, the phosphorus profile was altered. While this improved current and open circuit voltage, the use of aggressive screen printing paste shunted shallow junctions and significantly decreased the fill factor. The need for improved contact formation was evident for higher sheet resistance emitters developed in chapter 3, which has been done in chapter 4.In chapter 4, passivation and contacting of emitters developed in chapter 3 were improved with the introduction of thermal oxidation. Thermal oxide has been shown to improve i-PERC solar cell efficiency by 0.6-1.0% absolute. There are clear differences between improvements made on the front-side and the rear-side due to thermal oxide, the individual contributions of which are detailed in chapter 4. It has been shown that the gain in efficiency is largely attributed to the front-side. Careful selection of the emitter must be taken into account when attempting to enhance performance by oxidation. The recombination reduction is caused by the additional phosphorus drive-in and has been assessed separately from passivation enhancement achieved by the silicon oxide. Besides the expected improvement in open circuit voltage (passivation), the fill factor has also shown to improve. The improvement in fill factor is due to a significant (one order of magnitude) reduction in contact resistance in high sheet resistance (>85 Ω/□) emitters. This has been accredited to a large peak of phosphorus in the thermal oxide, which has been confirmed by SIMS and XPS measurements. Contact characterization by means of SEM, EDX, and C-AFM show that the large phosphorus content in the silicon oxide may improve crystallite formation or may form AgPx as detected by EDX. Phosphosilicate glass was used as an alternate method to introduce phosphorus in the passivation layer. Although PSG is not adequate for passivation, it has been shown to be able to enable a contact resistance below 3 mWcm² on a 95 Ω/□ emitter, which demonstrates the potential of phosphorus incorporation in passivation layers. The reliability and stability of the contacts has been assessed. Extended versions of the IEC61215s damp heat and thermal cycling tests have been performed. Phosphorus rich silicon oxide passivated i-PERC cells are shown to be as reliable as conventional screen printed cells.